This position is responsible for managing a circuit design team and a layout design team. The main design function is to provide circuit design blocks for chipset and graphic products; which includes PLL. DLL, DDR, DAC,VDS, RTC, SRAM, IO, and other Cerdes high speed I/O designs. The candidate must have hand-on design experience, and is able to provide design guidance to the design team. He/She is fully responsible for the quality outcome of team’s performance; required to define aggressive but realistic circuit/layout resource and task plan to support top down product roadmap; generate and track the team design execution plan on quarterly/weekly basis. In addition, this position is required to manage the team member’s career development and conduct individual’s performance evaluation.
【Requirements】:
1. 8+ years of hands on experience in custom/Analog IC design (80nm or below CMOS standard process is preferred) and has at least 4+ years of management experience;
2. Strong communication skills are required to guide, influence and convince others, in particular colleagues in other departments and external customers/agencies. Demonstrated ability to build strong relationships and mutual respect with the other function Departments and with any external partners;
3. Able to manage through first level managers or manage a group of "senior" level individual contributors. This includes management of people, defining roles and responsibilities, planning for the department’s operations, counseling employees on performance;
4. Experience with a full custom CMOS IC design project through the entire design cycle from concept to production release. Knowledge of high-speed IC design, analog and digital circuit design, latch-up, fabrication process fundamentals, layout floor planning and optimization;
5. Must familiar with Cadence design and layout environment and simulation tools;
6. PhD/MS in Science with major in Electrical Engineering or related fields, particularly, in the related fields of Analog circuit design.
