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 ██☞☞知名芯片公司高薪猎头职位---DV Manager/Electrical Analysis Engineer |
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milujite
头衔: 海归中士
加入时间: 2010/01/07
文章: 10
海归分: 636
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作者：milujite 在 海归招聘 发贴, 来自【海归网】 http://www.haiguinet.com
Position: DV Manager
Skills and Experience Requirements
- 10+ years of ASIC design and verification experience with minimum of 3+ years as DV technical lead/architect or manager position.
- Proven experience of the latest design verification methodology such as OVM, assertion ba<x>sed coverage driven verification (code & functional coverage), constraint random test generation, formal checking, power verification, modern design verification tools and languages (e.g. PSL/SVA, SystemC++, SystemVerilog, Vera, Specman, simulation systems)
- In depth experience in use of SystemVerilog and OVM to drive testbench is highly desirable
- In depth knowledge of ASIC design fundamentals from RTL to GDS including DFT verification.
- Working knowledge of x86 assembly programming is an asset.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- Proven debugging and problem analysis skills.
- Strong documentation and communication skills.
- Good people and project management skills including scheduling, resource allocation, risk assessment, matrix management, and process development and organized and methodical with proven ability to plan and execute project.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
JOB TITLE: Sr. Electrical Analysis Engineer
SKILLS REQUIRED
1) BS-EE / BS-CE and 3 years directly related experience. An advanced degree will be considered a plus.
2) Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR2/3 Memory, PCIx/PCIe or Hyper Transport Bus test experience on electronic components such as uProcessors would be considered a big plus.
4) Requires experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR & Hyper Transport
5) Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications.
6) Requires good written and oral communication skills. Demonstrate the ability to communicate with a variety of engineering disciplines and management.
以上职位工作地点均在上海，大家感兴趣可以点击我的用户名查看联系方式~
作者：milujite 在 海归招聘 发贴, 来自【海归网】 http://www.haiguinet.com
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 ██☞☞知名芯片公司高薪猎头职位---DV Manager/Electrical Analysis Engineer -- milujite - (2528 Byte) 2010-3-23 周二, 13:37 (1791 reads) - 顶 -- cschem8 - (1 Byte) 2010-4-15 周四, 15:40 (393 reads)
- 招聘继续 -- milujite - (19 Byte) 2010-4-06 周二, 10:06 (386 reads)
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